Efabless Announces Custom SoC Design Platform for Edge Machine Learning
Efabless marks chip manufacturing milestone
Nitin Dahad's interview (Editor in Chief of Embedded.com) with Mike Wishart at DAC 2024
Weebit Nano and Efabless collaborate to enable prototyping of SoC designs
Weebit Nano and Efabless hook up for prototyping
Weebit Nano and Efabless enable affordable SoC prototyping
Efabless to offer Weebit ReRAM memory at 130nm
Navigating the Semiconductor Revolution Fundings: Fourth Power, Doroni, Helicity Space
D&R Interview at DAC 2023 with Jeff DiCorpo - SVP and General Manager at Efabless
Mohamed Kassem | Circuit Talk: Funders and Founders
chipIgnite and OpenMPW Silicon Testing
How we fixed Caravel - An interview with Andy Wright
The OpenFPGA project and Open-source FPGA IPs | COSCUP x RubyConfTW 2021
Discussion Panel : the open way for making chips and its impact ! | COSCUP x RubyConfTW 2021
The Efabless Caravel project---Chip design for the software-oriented | COSCUP x RubyConfTW 2021
Special Issue Open Source EDA - March/April 2021 Issue of IEEE Design & Test
Cloud-based Automated SoC Design for an Intelligent Sensor, October 6th - 8th 2020
NEC Presentation at ChipEx2020
Open Core Summit 2020: December 16 -18, 2020.
CHiPS Alliance Workshop: Andrew Kahng, UC San Diego, and Mohamed Kassem, Efabless - OpenROAD Open RTL-to-GDS Update, September 17, 2020.
FOSSI Dial Up: Tim Edwards, Efabless: Using Magic for DRC checks on SkyWater 130nm, November 17, 2020.
FOSSI Dial Up; Mohamed Kassem, Efabless: The striVe RISC-V SoC Family on SkyWater 130nm, August 25, 2020.
FOSSI Dial Up: Mohamed Shalan, Efabless: OpenLane, A Digital ASIC Flow for SkyWater 130nm Open PDK, July 28, 2020.
FOSSI Dial Up: Tim Ansell, Google: Fully open source manufacturable PDK for a 130nm process; June 30, 2020.
Fabless Chip Design with Mohamed Kassem.
OSHW Panel, RISC-V Summit
WOSH Conference (Zürich) June, 2019 Day 1 talk: "Protecting proprietary data in an open environment"
WOSH Conference (Zürich) June, 2019 Day 2 talk: "Bootstrapping a real working design flow"
Protecting Proprietary Data in an Open Environment - Tim Edwards at FOSSI Foundation WOSH June 13, 2019 Zurich
Bootstrapping a Real Working Design Flow - Tim Edwards at FOSSI Foundation WOSH June 14, 2019 Zurich
Efabless' Raven: PicoRV32 on an ASIC, Open Source, Open Silicon Design - Mohamed Kassem & Tim Edwards RISC-V Workshop Zurich June 11-13, 2019 ETH Zurich
Efabless Corporation at IP SoC Santa Clara 2019
The Raven chip: First-time silicon success with qflow and Efabless, Tim Edwards, Open Circuit Design
Raven is Alive…Now Design Your Own on Efabless
1st Time Silicon Success with Open Source Tools
Arm Community and Cloud Enabling ASICs for IoT
How it Works? – Community Perspective
Community Engineering by Efabless
PicoSoc: How we created a RISC-V based ASIC processor using a full open-source foundry targeted RTL-toGDS flow, and how you can, too!
Go Configure Design Challenge Series promotional vide
Tim Edwards, SVP of Analog and Platform Efabless speaks at ORConf 2017 – Reinventing Harddware Innovation
![[object Object]](https://umsousercontent.com/lib_CUsguFEVafmoKCKW/ns6hm1s6vu8ctynd.png?w=334)
